1. Field of the Invention
The present disclosure relates generally to a semiconductor memory device and, more particularly, the present invention relates to a synchronous semiconductor memory device.
2. Description of the Related Art
Semiconductor memory devices form the bulk of memories used in computer systems. These memory devices usually include memory cells as the basic building blocks. In particular, data is input to these memory cells and data is output from these memory cells. The operating speeds of the computer systems depend on the speeds of the memory devices in the computer systems, which in turn depend on the speeds at which data are input to and output from these memory cells.
Various types of memory devices exist in the computer industry at this time. These types of devices include, for example, Dynamic Random Access Memory (DRAM) and Synchronous Dynamic Random Access Memory (SDRAM). SDRAM is generally considered to have higher operating speeds than DRAM. This is generally because, unlike DRAM, which is asynchronous, the SDRAM has a synchronous interface, meaning that it waits for a clock signal before responding to its control inputs. The clock is used to drive an internal finite state machine that pipelines incoming instructions. Because the instructions are pipelined, a SDRAM can receive a new instruction before completing a previous one.
Generally, a SDRAM uses column address strobe (CAS) latency to increase its operating frequency. CAS latency indicates the number of cycles of an external clock signal from when a read command is applied to a synchronous semiconductor memory device until data is output. The synchronous semiconductor memory device reads data stored therein in response to the read command and then outputs data after a number of clock cycles corresponding to the CAS latency. For example, when the CAS latency is 2, data is synchronized with an external clock signal 2 cycles after an external clock cycle in which a read command is applied. The read data is then output after the synchronization with the external clock signal.
Synchronization of the data with the external clock signal in a synchronous semiconductor memory device generally involves the use of a latency control circuit. In particular, a latency control circuit generates an output control signal, that is, a latency signal, in order to control data to be output from the synchronous semiconductor memory device after a predetermined number of cycles. In other words, the latency control circuit performs functions of an output control circuit. Specifically, after the read command is applied, the output control circuit provides the output control signal before a predetermined number of cycles of the output control clock signal in accordance with the CAS latency.
While the above-described operation of a synchronous semiconductor memory device increases operation speed, it includes various limitations. For example, as the operating frequency of the synchronous semiconductor memory device is increased, the sampling margin (or a timing margin) of an internal signal, such as a read information signal, in which a read command is decoded, is decreased. In addition, the sampling margin can be further decreased by process, voltage, and/or temperature variations or jitter in the synchronous semiconductor memory device.
This decrease of the sampling margin may affect the output control circuit, such that the output control circuit produces errors in the read data. As a result, the synchronous semiconductor memory device, including the output control circuit, may not output valid data.